1. Field of the Invention
The present invention relates to a coding assisting equipment and a decoding assisting equipment that are fed with information that is split into pieces having a predetermined word length and assist coding and decoding, respectively, of the information, as well as to the coding assisting equipment and the decoding assisting apparatus having such a coding assisting equipment or decoding assisting equipment.
2. Description of the Related Art
In recent years, a variety of digital modulation systems have been applied to mobile communication systems and other radio transmission systems to effectively utilize radio frequencies and realize high transmission rates.
At transmitting ends and receiving ends of such mobile communication systems, to secure desired transmission quality even in a state that the transmission characteristics of a radio transmission channel formed between a mobile station and a radio base station severely degrades, coding/decoding, interleave processing, and other processing that are adapted to such a radio transmission channel are performed.
FIG. 10 shows an example configuration of a coding part that is incorporated in a mobile station equipment.
In FIG. 10, a first output port of a processor (not shown) is connected to the input of a transmitter buffer 121. The output of the transmitter buffer 121 is connected to a parallel load terminal of a shift register 122. A clock terminal CL of the shift register 122, a read control terminal C of the transmitter buffer 121, and the output and a clock input CL of a counter 123 are connected to the corresponding input/output terminals of a controlling part 124. A second output port of the processor is connected to a reset terminal of the counter 123 and an activation input of the controlling part 124. A serial output of the shift register 122 is connected to a corresponding input of a CRC operation part 125, and the output of the CRC operation part 125 is connected to a modulation input of a transmitting part (not shown) via a convolutional coding part 126 and an interleaver 127. Corresponding outputs of the controlling part 124 are connected to respective control inputs of the CRC operation part 125 and the convolutional coding part 126.
The CRC operation part 125 is composed of a selector 128 one input of which is directly connected to the serial output of the shift register 122 and that is disposed as the final stage, an exclusive-OR gate 129 one input of which is directly connected to the serial output of the shift register 122 together with the one input of the selector 128, flip-flops (FFS) 130-1 and 130-2 that are cascaded to the output of the exclusive-OR gate 129, an exclusive-OR gate 131 one input of which is connected to the output of the exclusive-OR gate 129 together with the input of the flip-flop 130-1 and the other input of which is connected to the output of the flip-flop 130-2, and a flip-flop (FF) 130-3 the input of which is connected to the output of the exclusive-OR gate 131 and the output of which is connected to the other inputs of the exclusive-OR gate 129 and the selector 128.
The convolutional coding part 126 is composed of a cascade connection of flip-flops (FFs) 131-1 to 131-3 that is connected to the output of the CRC operation part 125 (selector 128), an exclusive-OR gate 132-1 having two inputs that are directly connected to the outputs of the respective flip-flops 131-1 and 131-2, an exclusive-OR gate 132-2 having two inputs that are directly connected to the outputs of the respective flip-flops 131-1 and 131-3, and a selector 133 that is disposed as the final stage and has two inputs that are connected to the outputs of the respective exclusive-OR gates 132-1 and 132-2.
In the above-configured conventional example, transmission information to be subjected to a CRC operation and convolutional coding (both described later) is stored in the transmitter buffer 121 collectively while being split by the processor into bytes. In the following description, such a series of processing performed by the processor to write transmission information to the transmitter buffer 121 will be referred to simply as “block transfer processing.”
When writing of all transmission information to the transmitter buffer 121 has completed, the processor feeds a reset signal to the counter 123 and the controlling part 124.
When receiving the reset signal, the counter 123 resets the count value, performs counting at a predetermined cycle, and sequentially outputs addresses as results of the counting.
When receiving the reset signal, the controlling part 124 supplies the selector 128 with a first selection signal indicating that “partial transmission information” (described later) should be selected, and resets the selector 133.
Every time the address that is output from the counter 123 is updated (including being initialized), the controlling part 124 commands the transmitter buffer 121 to read a byte (hereinafter referred to as “partial transmission information”) that is stored in a storage area corresponding to a new address among the storage areas of the transmitter buffer 121. Further, the controlling part 124 requests the shift register 122 to load the partial transmission information, and supplies the shift register 122 with a clock signal whose cycle is equal to ⅛ of the above-mentioned cycle.
The shift register 122 sequentially outputs already loaded partial transmission information bit-by-bit in synchronism with this clock signal.
In the CRC operation part 125, unless the above-mentioned first selection signal is updated, the selector 128 selects partial transmission information that is output serially from the shift register 122.
The exclusive-OR gates 129 and 131 and the flip-flops 130-1 to 130-3 generate an FCS (frame check sequence) to be added to the transmission information by dividing a sequence of the above-described partial transmission information by a generator polynomial G (x), which is given byG(x)=x3+x2+1. 
When the address that is output from the counter 123 has reached a predetermined value, the controlling part 124 identifies a point in time when the first bit of an FCS that conforms to the combination of the word length of the transmission information and the above-mentioned generator polynomial G (x) is obtained, updates the above-mentioned first selection signal, and fixes the logical value that is obtained at the output of the shift register 122 at “0.”
In the CRC operation part 125, when the first selection signal is updated, the selector 128 selects, instead of the partial transmission information, the FCS that is sequentially obtained in a serial manner via the flip-flop 130-3.
Therefore, a bit string consisting of the transmission information and the FCS that is added to the tail of transmission information end is obtained at the output of the selector 128 in a serial manner.
On the other hand, in the convolutional coding part 126, the selector 133 alternately selects the outputs of the exclusive-OR gates 132-1 and 132-2 at a frequency that is two times the bit rate of the above-mentioned bit string with the point in time of the resetting by the controlling part 124 employed as a reference.
The exclusive-OR gates 132-1 and 132-2 and the flip-flops 131-1 to 131-3 perform convolutional coding (rate of the code: ½; constraint length: 3) on the above-mentioned bit string by cooperating with the selector 133 while sequentially capturing the bit string bit-by-bit and performing predetermined logical operations.
The interleaver 127 sequentially captures and stores convolutional codes generated by the convolutional coding part 126 through the above convolutional coding. Further, the interleaver 127 performs, on the convolutional codes, interleave processing that is effective in reducing the degree of deterioration in transmission quality due to burst errors that may occur in the transmission channel by reading the stored convolutional codes bit-by-bit in predetermined order, and generates a transmission sequence.
That is, the CRC operation, the convolutional coding, and the interleave processing, which should be performed bit-by-bit in a serial manner to generate the transmission sequence, can be performed reliably and efficiently through involvement, only as an information source of transmission information, of a general-purpose processor that is generally not suitable for above kinds of bit-by-bit operations.
Incidentally, in the above conventional example, to start a CRC operation that should be performed prior to transmission of transmission information, the processor should perform the above-mentioned block transfer processing prior to the CRC operation.
Therefore, actually an individual piece of transmission information is not transmitted until after a lapse of time required for the block transfer processing (halftone-dot-meshed in FIGS. 11(A) and 11(B)) in addition to time required for the above-described CRC operation, convolutional coding, and interleave processing from a point in time when it is recognized, based on a channel control procedure etc., that the individual piece of transmission information should be transmitted.
For desired transmission information to be parallel/serial-converted on a partial transmission information basis through cooperation among the controlling part 124, the counter 123, and the shift register 133, it is necessary that the transmitter buffer 121 be of a type having a large hardware scale such as a dual port RAM, a FIFO, or a register file.
The longer the maximum word length of transmission information to be transmitted is, the larger the maximum information content that can be stored in the transmitter buffer 121 is. Therefore, depending on the channel control procedure, the channel allocation, the zone configuration, and other configurations, there is a possibility that the hardware scale of the transmitter buffer 121 accounts for most of that of the coding part of FIG. 10.
In general, the block transfer processing and the processor's processing of transmitting the above-mentioned reset signal are performed asynchronously with frames and slots that should be transmitted to a radio transmission channel. Therefore, if the CRC operation, the convolutional coding, and the interleave processing do not complete by the closest transmission time point that follows a point in time when the block transfer processing is started, the transmission of desired transmission information is deferred to the next transmission time point.
Technically, the parallel/serial conversion of transmission information that is performed in the above-described manner under the cooperation among the transmitter buffer 121, the shift register 122, the counter 123, and the controlling part 124 can be realized as processing performed by the processor. However, in general, the processor is required to perform, on a real-time basis, many kinds of processing that should be completed in predetermined periods, such as a channel control. Therefore, it is necessary that the above-mentioned CRC operation, convolutional coding, and interleave processing be performed by dedicated hardware that is provided to reduce the load of the processor.
Where the response speeds of the shift register 122, the counter 123, the controlling part 124, the CRC operation part 125, the convolutional operation section 126, and the interleaver 127 are sufficiently high, it is possible to increase the efficiency of coding and reduce the hardware size by directly loading, into the shift register 122, skipping the transmitter buffer 121, pieces of partial transmission information that are sequentially fed from the processor.
However, to realize a reliable operation for the maximum speed (e.g., 16 MHz) at which the processor can feed partial transmission information, the CRC operation part 125 needs to respond at a speed (128 MHz) that is eight times faster than the above speed and the convolutional coding part 126 and the interleaver 127 need to respond even two times faster (256 MHz).
Realization of circuits capable of operating at such high speeds is prevented by price-related limitations. Even if such limitations are overcome, limitations relating to the thermal designing and the mounting technology still prevent realization of such circuits because of large increase in power consumption.
This problem could be solved by giving higher priority to the block transfer processing and the processing of outputting a reset signal, of processes performed by the processor, or by making the speed at which partial transmission information is fed lower than a predetermined value.
However, if such a measure is taken, in addition to the task (process) configuration that is the structure of processes to be executed by the processor, methods (synchronization among the tasks, communication, etc.) that realize cooperation among the tasks and the combination of these methods would be refined. Therefore, the timing of processes that do not relate to the above problem may also change.